Integrated circuits and semiconductor devices are fabricated by performing a number of fabrication processes that form various components and regions, such as source/drain regions, gate structures, isolation regions, and the like. One set of structures formed and/or present in semiconductor devices are metallization layers, which provide electrical connections between various components within the devices and external connections.
The metallization layers typically comprise trenches and vias formed in single or dual damascene fabrication processes. The trenches and vias are comprised of conductive materials and are separated by insulating layers comprised of dielectric material to, for example, mitigate crosstalk between various layers. The trenches and vias form interconnects or pathways through the dielectric material.
The yield and reliability of fabricated semiconductor devices is dependent upon the single or dual damascene fabrication processes employed to form the metallization layers. Defects in the metallization layers can be formed or introduced during the damascene fabrication processes and degrade the overall yield and reliability of semiconductor devices.
One type of defect that can be found in metallization layers is a punch thru defect, which is a region of missing copper in a metal level that is undesirably removed. The punch thru defects can degrade device performance by, for example, increasing resistance or preventing electrical connections.